MIT scientists innovate to create more powerful and denser computer chips

“The new capability of low thermal budget growth on an 8-inch scale enables the integration of this material with silicon CMOS technology and paves the way for its future electronics application.”
Amal Jos Chacko
A computer chip.jpg
A computer chip.


With our pockets and houses filling with electronic gadgets and AI and Big Data fueling the rise of data centers, there is a need for more computer chips— more powerful, potent, and denser than ever. 

These chips are traditionally made with boxy 3D materials bulky in nature, making stacking these into layers difficult. 

However, transistors could be made from 2D ultrathin materials, solving this stacking challenge. These 2D materials are typically grown elsewhere and then transferred onto the chip or wafer— an imperfect procedure that makes these transistors vulnerable to inconsistent and hampered performance.

An interdisciplinary team of MIT researchers has revealed the development of a new technology that can grow layers of these 2D materials directly on top of fully fabricated silicon chips in a paper released in the peer-reviewed scientific journal Nature Nanotechnology

Their new process makes it possible to grow smooth and uniform layers across 8-inch wafers while significantly reducing the time required. This new method could be pivotal in commercial applications where wafers larger than 8 inches are typical.

Jiadi Zhu, electrical engineering and computer science graduate student and co-lead author of the paper, broke the technique down into simpler terms. “Using 2D materials is a powerful way to increase the density of an integrated circuit. What we are doing is like constructing a multistory building. If you have only one floor, it won’t hold many people. But with more floors, the building will hold more people that can enable amazing new things. Thanks to the heterogeneous integration we are working on, we have silicon as the first floor and then we can have many floors of 2D materials directly integrated on top,” he said.

MIT scientists innovate to create more powerful and denser computer chips
Jiadi Zhu holding an 8-inch CMOS wafer with molybdenum disulfide thin film. On the right is the furnace the researchers developed.

Zhu and his team focused on molybdenum disulfide, a flexible and transparent 2D material exhibiting powerful electronic and photonic properties, making it optimal for semiconductor transistors.

Thin molybdenum disulfide films are generally grown through a metal-organic chemical vapor deposition (MOCVD) process. This reaction involves decomposing molybdenum and sulfur compounds at temperatures above 1022 degrees Fahrenheit (550 degrees Celsius). But silicon circuits degrade as temperatures surpass 752 degrees Fahrenheit (400 degrees Celsius).

The researchers designed and built a new furnace for the decomposition process to combat this degradation. The oven consists of two chambers: the front, a low-temperature region where the silicon wafer is placed, and the back, a high-temperature region. Vaporized molybdenum and sulfur compounds then get pumped into the furnace. 

While molybdenum stays and decomposes at the front, where temperatures are below 752 degrees Fahrenheit, the sulfur compound flows into the hotter rear, where it decomposes.

On decomposition, it flows back into the front and chemically reacts to grow molybdenum disulfide on the surface of the wafer.

Zhu and the team now look to fine-tune their technique and explore similar processes to grow these layers into everyday surfaces like textiles and paper.

Study Abstract

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS2) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm2 V−1 s−1. Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

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